DAK 9 PLL Unlock Issue

[BBB]

My recently acquired DAK MARK IX has an apparent issue with the PLL unlocking when the channel selector is moved or touched. Simply powering down and back on brings the PLL back on line. It's just frustrating to have to do this every time I want to change the channel.

When I brought this up before, Sandbagger was gracious in mentioning that there may be a PLL Inhibit wire or mode that may be causing the problem. If I understand it correctly, in some CB radios, this inhibit mode was so that you couldn't slide the channel selector in between channels and go out of the FCC approved band plan for 11 meters.

I have read elsewhere that the DAK IX is prone to channel selector failure, but it wasn't mentioned as to what the common failure mode was. All the LED segments display fine. This radio was modded by the previous owner for extra channels and a 10K switch. Interestingly, it only has an added switch for lower channels. The ANL switch was combined with the noise blanker circuit and the noise blanker switch is now used for the 10K switch. I tried spraying some De-Oxit on the channel selector switch but it's sealed pretty well in a metal can. I guess I could remove the channel selector board and open up the can if required to try and repair it.

I was wondering if anyone could take a peak at the attached schematic and MC145106 PLL sheet to point me in the right direction as to what to look for as far as correcting the PLL unlock issue. Might be as simple as disabling the PLL inhibit wire/ mode somehow? Fortunately, the radio and MC145106 PLL chip are well documented. Thanks in advance.

PLL CHIP data sheet:

www.cbtricks.com/radios/galaxy/datasheets/ic/pdf/mc145106.pdf

DAK IX PLL board schematic:

www.cbtricks.com/radios/dak/mark_ix/graphics/dak_markIX_pll_sch.gif

DAK IX schematic:

www.cbtricks.com/radios/dak/mark_ix/graphics/dak_markIX_main_sch.gif

[BBB]

On the PLL chip:

LD
Lock Detector (PDIP, SOG — Pin 8)
LD is high when loop is locked, pulses low when out–of–
lock

??This would just send a signal that the PLL was unlocked as a warning to something?

φDetout (PDIP, SOG — Pin 7)
Signal for control of external VCO, output high when f
in /N is less than the reference frequency; output low when f
in /N is greater than the reference frequency. Reference frequency is
the divided down oscillator — input frequency typically 5.0 or
10 kHz.

This detector section would maybe be the issue?

[Sandbagger]

Jan 3, 2018 12:35:19 GMT -5 BBB said:

On the PLL chip:

LD
Lock Detector (PDIP, SOG — Pin 8)
LD is high when loop is locked, pulses low when out–of–
lock

??This would just send a signal that the PLL was unlocked as a warning to something?

φDetout (PDIP, SOG — Pin 7)
Signal for control of external VCO, output high when f
in /N is less than the reference frequency; output low when f
in /N is greater than the reference frequency. Reference frequency is
the divided down oscillator — input frequency typically 5.0 or
10 kHz.

This detector section would maybe be the issue?

Well, based on what I was able to glean from the schematics, there does not appear to be a physical "inhibit" mechanism on the channel selector itself. There is only the inhibit that comes from the PLL lock detect output. The way the circuit is configured, if the LD pin reflects a PLL unlock condition, it will pull low which will cut power to the TX buffer stage and prevent transmission. But it should have no effect on receive. So if your receive is blanking out as well, the problem isn't with the LD circuit. You could have a situation where the channel selector is momentarily putting out a code which the PLL can't handle (but it should) when you touch it, and it unlocks. You should be able to measure pin 8 to see if it's in a low (~0V) state, and the phase detector output (pin 7) is at either a 0V or 5V rail. That pretty much tells the story of a PLL that's out of lock. You should then try measuring all of the control pins that are connected to the selector to make sure that they are providing the proper binary code for the channel you're on. The VCO may need to be adjusted if it's running too high or low on pin 7 when it's operating properly and locked. Ideally, for a ballpark figure, the VCO voltage should be 2.5 - 3V on the legal 40. The fact that someone put extra channels in it, probably means that they probably adjusted the VCO to cover either higher or lower channels and it may be a bit squirrelly on the regular channels.

[2600]

We had an issue with the PLL locking range on this radio when they were being sold new. Not every one did this, and I don't know which serial numbers had it. The PLL would maintain proper lock for only 10 or 20 channels. Moving the slug in the VCO coil would move the range of channels up and down, but you could still get only half or less of the whole 40 channels.

The fix was to cut the foil trace at pin 2 of the PLL chip. A 100pf disc capacitor would go across the cut in the foil.

Pretty sure it was 100 pf. Been a while since seeing the last one of those with this issue.

When word got out we had cracked this nut, a half-dozen of these radios made their way to our shop in the next couple of weeks.

Might fix your problem. If L404 is not peaked, this can make the PLL twitchy about maintaining a lock. Watching pin 2 with a 'scope and peaking L404 for max signal at that pin is the best way to be sure.

73

[BBB]

Thank you for the replies. I will dig a bit deeper and try to get the Channel Selector / PLL to stabilize.